Sr.RTL Design Engineer ( IP )

☞ Mobiveil Technologies India Private Limited

View: 103

Update day: 31-10-2023

Location: Hyderabad / Secunderabad Telangana

Category: Electrical / Electronics

Industry:

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Job content

Job Description


Roles and Responsibilities


  • 4-8 years of experience in ASIC and/or FPGA design
  • Experience in ASIC/FPGA IP development - Architecture, Microarchitecture.
  • Able to Perform RTL coding, Debugging in simulation and hardware, LINT/CDC, DC Synthesis
  • Proficient in Synthesizable and parameterized RTL coding using Verilog Language
  • Experience with synthesis and static timing tools on ASIC/FPGA
  • Experience in protocols such as PCI-Express, NVM Express, DDR, RapidIO is a plus and preferred.
  • Candidate should be Self Motivated, Proactive and should have attention to detail
  • Should be able to clearly communicate with other teams/team members on a day-to-day basis.

Role:
Technical Lead -Hardware Design
Salary:
Not Disclosed by Recruiter
Industry:
Electronic Components / Semiconductors
Functional Area
IT Hardware, Technical Support, Telecom Engineering
Role Category
IT Hardware
Employment Type:
Full Time, Permanent
Key Skills

ASIC

FPGA Design

Ddr

Verilog

Scripting Languages

ip

Perl

TCL

RTL Design

Logic Design

Education-
UG:
Any Graduate
PG:
Post Graduation Not Required
Doctorate:
Doctorate Not Required

Company Profile

Mobiveil Technologies India Private Limited
A brief intro about Mobiveil

Mobiveil Inc is a fast growing technology company that delivers Silicon IPs and platform enabled solutions to semiconductor companies, OEMs, and design houses. Over the past 7 years, we had grown a solid team in Hardware/Embedded Software, Protocol Stack Development, ASIC Services & Testing Services. We also have a small team on Network protocol implementations.

from 4 to 9 year(s) of Experience
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Deadline: 15-12-2023

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